Field
The disclosure relates generally to a dc-to-dc voltage converter and, more particularly, to an switching converter circuits with improved efficiency at light load conditions thereof.
Description of the Related Art
Switching converters for battery operated systems are required to source load currents. The load currents of interest are from a range of 0 to 10 A. Additionally, the converter has to sustain an excellent power efficiency and be able to support load current switching from 0 A to the maximum current, Imax, with a minimum output voltage ripple.
As an example, FIG. 1 highlights the sources of power loss for a synchronous buck converter. In heavy load operation, the conduction losses dominate. FIG. 1. shows a synchronous buck converter 100. The synchronous buck converter 100 comprises a p-channel metal oxide semiconductor field effect transistor (MOSFET) 110 and a n-channel MOSFET 120. A pre-drive includes a p-channel MOSFET pre-drive circuit 115 and n-channel MOSFET pre-drive circuit 125. The synchronous inverter circuit includes an inductor 130 and capacitor 140. The output includes a load 150. The input has a power supply Vin 160 in parallel with an input capacitor 165. A feedback loop electrically couples the output vout(t) with a Controller 170, which feeds a signal to the pre-drive elements 115 and 125.
The conduction losses as highlighted in FIG. 1 include the MOSFET switching and conduction losses of the p-channel MOSFET device 110, and body-diode losses of the n-channel MOSFET 120. The losses from the passive elements include the electrical series resistance (ESR) loss of the input capacitor, 165, the electrical series resistance (ESR) of the inductor 130, and the electrical series resistance (ESR) loss of the output capacitor 140.
Therefore, metal oxide semiconductor field effect transistors (MOSFETs) with low on-resistance (Ron) and a low electrical series resistance (ESR) inductor are needed to meet efficiency specifications. However under light-load conditions, MOSFET switching and gate-drive losses become significant, especially for integrated converters with operation frequency beyond several MHz. As a result, the efficiency degrades as the load current decreases. Light-load efficiency is a major concern in applications where the digital load ICs spend the majority of their time in idle mode.
Various techniques have been presented in order to reduce switching losses in light-load condition, which can be classified in two categories: variable frequency techniques and adaptive output stages.
Variable frequency techniques include pulse frequency modulation (PFM), pulse-skip (PS), and burst-mode control. The disadvantage of these techniques is that they generally lead to poor output voltage regulation due to the load dependence of source frequency (fs). These variable frequency techniques also have a concern with electromagnetic interference (EMI).
In the adaptive output stage technique, the switching converter output stage is defined as segments (e.g. or also referred to as fingers) wherein portions of the adaptive output stage can be turned off at light-load conditions to optimize the trade-off between the effective gate capacitance and the on-resistance, rON. This is also known as the “switched-width” concept. Segmentation is practically achieved by separating the MOSFET gate structure of power MOSFET cells in the physical design layout, while the MOSFET drain and source metallization pattern remains unchanged.
FIG. 2A shows a circuit schematic of segmented output stage 200. The circuit in FIG. 2A comprises of a power stage with MOSFET of various widths providing segmentation illustrated by example as 210 (i), 210 (j), 210 (k) to 210 (n). The logic gates 230 (i), 230 (j), 230 (k) to 230 (n), are electrically coupled to the power stage of MOSFETs 210 (i), 210 (j), 210 (k) to 210 (n). The output of the power stage is connected to inductor 240, capacitive load 250, resistive load 260 with an output signal 280. The input signal 270 is connected to the logic gates 230 (i) to 230 (n).
The typical implementation of an adaptive output stage is monitoring the output current and setting the number of active stages using a pre-defined load current threshold, which are previously calculated values for typical operation parameters. Similarly, switching from synchronous mode to PFM mode is usually defined by a pre-defined load current threshold. However, various other operation condition dimensions also have to be considered. For example, switching losses are not a constant magnitude; it is a function of input voltage (which can change more than two orders of magnitude), gate capacitance and operating frequency.
Assuming these parameters are constant throughout the circuit operation, the parameters will cause significant errors deviating the system from operating with optimal efficiency. In addition, the effects such as aging, process variations or temperature significantly affect switch transistor “on resistance” (rON); this can generate estimation errors (e.g. on resistive losses), which all result in non-optimal efficiency for the switching converter.
U.S. Pat. No. 8,618,783 to Oki, describes a DC-to-DC converter with a method of adaptive phase compensation.
In IEEE Custom Integrated Circuits Conference to S. Kudva, S. Chaubey, and R. Harjani, titled “High Power-Density Hybrid Inductive/Capacitive Converter with Area Reuse for Multi-domain DVS,” (September 2014), describes a converter with inductive converter for large loads, and capacitive converter for lower loads.
In IEEE Custom Integrated Circuits Conference to R. Harjani and S. Chaubey, titled “A Unified Framework for Capacitive Series-Parallel DC-DC Converter Design,” (September 2014), describes methods for DC-DC conversion.
U.S. Pat. No. RE44587 E1 to Qui et al, describes a dc-dc converter with a drive stage that is adaptive.
In IEEE Power Electronics Letters, to S. Musunuri and P. Chapman, titled “Improvement of Light-Load Efficiency Using Width-Switching Scheme for CMOS Transistors,” IEEE Power Electronics Letters, Vol. 3, pp. 105-110 (September 2005), describes a method of width switching that utilizes segmentation of the output stage for light load efficiency.
In Journal of Solid State Circuits, to S. Kudva and R. Harjani, titled “Fully-Integrated On-Chip DC-DC Converter With a 450× Output Range,” JSSC, Vol. 46, No. 8, pp. 1940-1951, August 2011, describes an apparatus with a wide power range for dynamic voltage scaling (DVS).
In these prior art embodiments, the solution to establish a sampling circuit in switching regulator utilized various alternative solutions.